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datasheet 9DBV0431 revision c 11/26/14 1 ?2014 integrated device technology, inc. 4 o/p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 description the 9DBV0431 is a member of idt's soc-friendly 1.8v very-low-power (vlp) pcie family. it can also be used for 50m or 125m ethernet applications via software frequency selection. the device has 4 output enables for clock management, and 3 selectable smbus addresses. recommended application 1.8v pcie gen1-2-3 zero-del ay/fan-out buffer (zdb/fob) output features ? 4 - 1-200hz low-power (lp) hcsl dif pairs w/z o =100ohms key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms for 12k-20mhz features/benefits ? lp-hcsl outputs save 8 resistors; minimal board space and bom cost ? 53mw typical power consumption in pll mode; minimal power consumption ? oe# pins; support dif power management ? hcsl compatible differential input; can be driven by common clock sources ? programmable slew rate for each output; allows tuning for various line lengths ? programmable output amplitude; allows tuning for various application environments ? pin/software selectable pl l bandwidth and pll bypass; minimize phase jitter for each application ? outputs blocked until pll is locked; clean system start-up ? software selectable 50mhz or 125mhz pll operation; useful for ethernet applications ? configuration can be accomplished with strapping pins; smbus interface not required for device control ? 3.3v tolerant smbus interface works with legacy controllers ? space saving 32-pin 5x5mm vfqfpn; minimal board space ? selectable smbus addresses; multiple devices can easily share an smbus segment block diagram clk_in dif(3:0) control logic sadr_tri ckpwrgd_pd# zdb pll 4 oe(3:0)# hibw_bypm_lobw# clk_in# s d a t a _ 3 . 3 s c l k _ 3 . 3
4 o/p 1.8v pcie gen1-2-3 zdb/fob 2 revision c 11/26/14 9DBV0431 datasheet pin configuration smbus address selection table power management table ^sadr_tri ^ckpwrgd_pd# gnd voe3# dif3# dif3 gnd vddo1.8 32 31 30 29 28 27 26 25 ^vhibw_bypm_lobw# 1 24 voe2# fb_dnc 2 23 dif2# fb_dnc# 3 22 dif2 vddr1.8 4 21 vdda1.8 clk_in 5 20 gnda clk_in# 6 19 dif1# gndr 7 18 dif1 gnddig 817voe1# 9 10111213141516 vdddig1.8 sclk_3.3 sdata_3.3 voe0# dif0 dif0# gnd vddo1.8 32-pin vfqfpn, 5x5 mm, 0.5mm pitch v prefix indicates internal 120kohm pull down resistor 9DBV0431 ^ prefix indicates internal 120kohm pull up resistor ^v prefix indicates internal 120kohm pull up and pull down resistor ( biased to vdd/2 ) sadr address 0 1101011 m 1101100 1 1101101 x state of sadr on first application of ckpwrgd_pd# + read/write bit x x true o/p comp. o/p 0 x x x low low off 1 running 0 x low low on 1 1 running 1 0 running running on 1 1 running 1 1 low low on 1 clk_in oex# pin pll difx ckpwrgd_pd# smbus oex bit 1. if bypass mode is selected, the pll will be off, and outputs will be running.
revision c 11/26/14 3 4 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 datasheet power connections frequency select table pll operating mode vdd gnd 47 98 16, 25 15,20,26,30 21 20 input receiver analo g digital power dif outputs pll analog description pin number fsel b y te3 [ 4:3 ] clk_in ( mhz ) difx ( mhz ) 00 (default) 100.00 clk_in 01 50.00 clk_in 10 125.00 clk_in 11 reserved reserved hibw_bypm_lobw# mode byte1 [7:6] readback byte1 [4:3] control 0 pll lo bw 00 00 mbypass0101 1 pll hi bw 11 11
4 o/p 1.8v pcie gen1-2-3 zdb/fob 4 revision c 11/26/14 9DBV0431 datasheet pin descriptions pin# pin name type pin description 1 ^vhibw_bypm_lobw# latched in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for details. 2 fb_dnc dnc true clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 3 fb_dnc# dnc complement clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 4 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 5 clk_in in true input for differential reference clock. 6 clk_in# in complementary input for differential reference clock. 7 gndr gnd analog ground pin for the differential input (receiver) 8 gnddig gnd ground pin for digital circuitry 9 vdddig1.8 pwr 1.8v digital power (dirty power) 10 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 11 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 12 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 13 dif0 out differential true clock output 14 dif0# out differential complementary clock output 15 gnd gnd ground pin. 16 vddo1.8 pwr power supply for outputs, nominally 1.8v. 17 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 gnda gnd ground pin for the pll core. 21 vdda1.8 pwr 1.8v power for the pll core. 22 dif2 out differential true clock output 23 dif2# out differential complementary clock output 24 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 vddo1.8 pwr power supply for outputs, nominally 1.8v. 26 gnd gnd ground pin. 27 dif3 out differential true clock output 28 dif3# out differential complementary clock output 29 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 gnd gnd ground pin. 31 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 32 ^sadr_tri latched in tri-level latch to select smbus address. see smbus address selection table.
revision c 11/26/14 5 4 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 datasheet test loads driving lvds rs rs low-power differential output test load 2pf 2pf 5 inches zo=100ohm alternate differential output terminations rs zo units 33 100 27 85 ohms lvds clk input l4 r8b r7b r8a r7a 3.3 volts cc cc rs rs driving lvds driving lvds inputs with the 9DBV0431 receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note
4 o/p 1.8v pcie gen1-2-3 zdb/fob 6 revision c 11/26/14 9DBV0431 datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9DBV0431. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaran teed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes power supply voltage vddxx applies to all vdd pins -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.5v v 1, 3 input high voltage, smbus v ihsmb smbus clock and data pins 3.6v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes input high voltage - dif_in v i hdi f differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 725 mv 1 input amplitude - dif_in v swing peak to peak value (vihdif - vildif), single-ended 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 150 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero
revision c 11/26/14 7 4 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes 1.8v supply voltage vdd supply voltage for core, analog and lvcmos outputs 1.7 1.8 1.9 v 1 t com commmercial range 0 25 70 c 1 t ind industrial range -40 25 85 c 1 input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v 1 input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4 v dd 0.6 v dd v1 input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v1 schmitt trigger postive going threshold voltage v t+ single-ended inputs, where indicated 0.4 v dd 0.7 v dd v1 schmitt trigger negative goin g threshold volta g e v t- single-ended inputs, where indicated 0.1 v dd 0.4 v dd v1 hysteresis voltage v h v t+ - v t- 0.1 v dd 0.4 v dd v1 output high voltage v ih single-ended outputs, except smbus. i oh = -2ma v dd -0.45 v 1 outputt low voltage v il single-ended outputs, except smbus. i ol = -2ma 0.45 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp bypass mode 1 200 mhz 2 f i p ll100 100mhz pll mode 50 100 150 mhz 2 f i p ll125 125mhz pll mode 62.5 125 170 mhz 2 f i p ll62 50mhz pll mode 25 50 70 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,6 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.6 1 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 31.5 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 175 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 1,2 trise t r rise time of single-ended control inputs 5 ns 1,2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.8 v 1,4 smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.6 v 1,5 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 1.7 3.6 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 1,7 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until outputs are >200 mv 6 dif_in input 7 the differential input clock must be running for the smbus to be active 4 for v ddsmb < 3.3v, v ilsmb <= 0.25v ddsmb 5 for v ddsmb < 3.3v, v ihsmb >= 0.7v ddsmb ambient operating temperature input current input frequency capacitance
4 o/p 1.8v pcie gen1-2-3 zdb/fob 8 revision c 11/26/14 9DBV0431 datasheet electrical characteristics?dif 0.7v low power hcsl outputs electrical characteristi cs?current consumption ta = t com or t i nd; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope averaging on 3.0v/ns setting 2 3.2 4 v/ns 1, 2, 3 scope averaging on 2.0v/ns setting 1.3 2.3 3.3 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 5.4 20 % 1, 2, 4 voltage high v hi gh 660 779 850 1,7 voltage low v low -150 21 150 1,7 max voltage vmax 835 1150 1 min voltage vmin -300 -42 1 vswing vswing scope averaging off 300 1515 mv 1,2,7 crossing voltage (abs) vcross_abs scope averaging off 250 409 550 mv 1,5,7 crossing voltage (var) -vcross scope averaging off 14 140 mv 1, 6 2 measured from differential waveform slew rate trf statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 7 at default smbus settings. 1 guaranteed by design and characterization, not 100% tested in production. c l = 2pf with r s = 33 ? for zo = 50 ? (100 ? differential trace impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting ? - vcross to be smaller than vcross absolute. ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddrop vddr, @100mhz 4.2 6 ma 1 i ddop vdda + vdd1.8, @100mhz 27 33 ma 1 i ddrop vddr, @100mhz 2.2 3 ma 1 i ddop vdda + vdd1.8, @100mhz 20 25 ma 1 i ddrpd vddr, ckpwrgd_pd# = 0 0.014 0.3 ma 1,2 i ddpd vdda + vdd1.8, ckpwrgd_pd# = 0 0.95 1.2 ma 1, 2 1 guaranteed by design and characterization, not 100% tested in production. 2 input clock stopped, and ckpwrgd_pd# pin low. operating supply current (pll mode) operating supply current (pll-bypass mode) powerdown current
revision c 11/26/14 9 4 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 datasheet electrical characteristics?ou tput duty cycle, jitter, sk ew and pll characteristics electrical characteristics? phase jitter parameters ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes -3db point in high bw mode 2 2.7 4 mhz 1,5 -3db point in low bw mode 1 1.4 2 mhz 1,5 pll jitter peaking t jpeak peak pass band gain 1.2 2 db 1 duty cycle t dc measured differentially, pll mode 45 50.1 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -1 -0.1 1 % 1,3 t p dbyp bypass mode, v t = 50% 2550 3370 4200 ps 1 t p dpll pll mode v t = 50% 0 112 200 ps 1,4 commercial operating range, v t = 50% 33 50 ps 1,4 industrial operating range, v t = 50% 33 55 ps 1,4 pll mode 13 50 ps 1,2 additive jitter in bypass mode 0.1 1 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform 3 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. 4 all outputs at default slew rate 5 the min/typ/max values of each bw setting track each other, i.e., low bw max will never occur with hi bw min. pll bandwidth bw skew, input to output skew, output to output t sk3 jitter, cycle to cycle t jcyc-cyc ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jp hpcieg1 pcie gen 1 32 52 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.8 1.4 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.4 2.6 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.5 0.6 1 ps (rms) 1,2,4 t jphsgmii 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 1.9 2.2 3 ps (rms) 1,6 t jphpcieg1 pcie gen 1 0.1 5.0 n/a ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.2 0.3 n/a ps (rms) 1,2,4 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.05 0.1 n/a ps (rms) 1,2,4 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.05 0.1 n/a ps (rms) 1,2,4 t jphsgmiim0 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 165 200 n/a fs (rms) 1,6 t jphsgmiim1 125mhz, 12khz to 20mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 251 300 n/a fs (rms) 1,6 1 guaranteed by design and characterization, not 100% tested in production. 4 for rms figures, additive jitter is calculated by solving the following equation: additive jitter = sqrt[(total jitter)^2 - (i nput jitter)^2] 5 driven by 9fgv0831 or equivalent 6 driven by rohde&schwarz sma100 additive phase jitter, bypass mode t jphpcieg2 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. phase jitter, pll mode t jphpcieg2
4 o/p 1.8v pcie gen1-2-3 zdb/fob 10 revision c 11/26/14 9DBV0431 datasheet additive phase jitter plo t: 125m (12khz to 20mhz)
revision c 11/26/14 11 4 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: smbus address is latched on sadr pin. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) id t (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
4 o/p 1.8v pcie gen1-2-3 zdb/fob 12 revision c 11/26/14 9DBV0431 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 1 bit 6 dif oe3 output enable rw low/low enabled 1 bit 5 dif oe2 output enable rw low/low enabled 1 bit 4 1 bit 3 dif oe1 output enable rw low/low enabled 1 bit 2 1 bit 1 dif oe0 output enable rw low/low enabled 1 bit 0 1 1. a low on these bits will overide the oe# pin and force the differential output low/low smbus table: pll operating mode and output amplitude control register byte 1 name control function type 0 1 default bit 7 pllmoderb1 pll mode readback bit 1 r latch bit 6 pllmoderb0 pll mode readback bit 0 r latch bit 5 pllmode_swcntrl enable sw control of pll mode rw values in b1[7:6] set pll mode values in b1[4:3] set pll mode 0 bit 4 pllmode1 pll mode control bit 1 rw 1 0 bit 3 pllmode0 pll mode control bit 0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 1 bit 6 slewratesel dif3 slew rate selection rw 2 v/ns 3 v/ns 1 bit 5 slewratesel dif2 slew rate selection rw 2 v/ns 3 v/ns 1 bit 4 1 bit 3 slewratesel dif1 slew rate selection rw 2 v/ns 3 v/ns 1 bit 2 1 bit 1 slewratesel dif0 slew rate selection rw 2 v/ns 3 v/ns 1 bit 0 1 smbus table: frequency select control register byte 3 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 freq_sel_en enable sw selection of frequency rw sw frequency change disabled sw frequency change enabled 0 bit 4 fsel1 freq. select bit 1 rw 1 0 bit 3 fsel0 freq. select bit 0 rw 1 0 bit 2 1 bit 1 1 bit 0 slewratesel fb adjust slew rate of fb rw 2 v/ns 3 v/ns 1 1. b3[5] must be set to a 1 for these bits to have any effect on the part. byte 4 is reserved and reads back 'hff see pll operating mode table reserved see pll operating mode table reserved see frequency select table controls output amplitude reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
revision c 11/26/14 13 4 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 1 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 1 bit 1 device id1 r 0 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 000100 binary or 04 hex 00 = fgv, 01 = dbv, 10 = dmv, 11= reserved byte count programming a rev = 0000 revision id 0001 = idt device type writing to this register will configure how many bytes will be read back, default is = 8 bytes. reserved reserved vendor id device id reserved
4 o/p 1.8v pcie gen1-2-3 zdb/fob 14 revision c 11/26/14 9DBV0431 datasheet marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?coo? denotes country of origin. 3. yyww is the last two digits of the ye ar and week that the part was assembled. 4. line 2: truncated part number 5. ?l? denotes rohs compliant package. 6. ?i? denotes industrial temperature range device. thermal characteristics ics bv0431al yyww coo lot ics b0431ail yyww coo lot parameter symbol conditions pkg typ value units notes jc junction to case 42 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 1 epad soldered to board nlg32 thermal resistance
revision c 11/26/14 15 4 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0431 datasheet package outline and package dimensions (nlg32) ordering information "lf" suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with the datasheet revision). millimeters symbol min max a0.801.00 a1 0 0.05 a3 0.20 reference b 0.18 0.3 e 0.50 basic d x e basic 5.00 x 5.00 d2 min./max. 3.00 3.30 e2 min./max. 3.00 3.30 l min./max. 0.30 0.50 n32 n d 8 n e 8 anvil singulation -- or -- sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 part/order number shipping packaging package temperature 9DBV0431aklf trays 32-pin vfqfpn 0 to +70 c 9DBV0431aklft tape and reel 32-pin vfqfpn 0 to +70 c 9DBV0431akilf trays 32-pin vfqfpn -40 to +85 c 9DBV0431akilft tape and reel 32-pin vfqfpn -40 to +85 c
4 o/p 1.8v pcie gen1-2-3 zdb/fob 16 revision c 11/26/14 9DBV0431 datasheet revision history rev. initiator issue date description page # a rdw 8/13/2012 1. removed "differential" from ds title and recommended application, corrected typo's in description. 2. corrected spelling error in pullup/pulldown text under pinout 3. updated all electrical tables and added "industry limit" column to "phase jitter parameters". 4. updated byte3[0] to be consistent with byte 2. updated byte6[7:6] definition. 5. added thermal data to page 12. 6. added nlg32 to "package outline and package dimensions" on page 13. 7. move to final 1,2,5- 8,10, 12,13 b rdw 2/28/2013 1. "input/supply/common parameters" table modified as follows: a. updated single-ended input logic thresholds to include missing mid-level on tri-level inputs. adjusted logic thresholds as follows: i. changed vih min. from 0.65*vdd to 0.75*vdd ii. changed vil max. from 0.35*vdd to 0.25*vdd iii. added missing mid-level input voltage spec (vim) of 0.4*vdd to 0.6*vdd. iv. clarified conditions for these specifications, accordingly. b. clarified the operating conditions and voltages of the smbus to make it clear that the smbus operates at <3.3v by addition of footnotes 4 and 5 to "input/supply/common parameters" table. 2. slight modifications of slew rates and typical values in the "dif 0.7v low power differential outputs" table. 3. "current consumption" table modifed as follows: a. overall current consumption values lowered b. vdda is now grouped with vdd1.8 instead of vddr c. added separate current specs for pll bypass mode. d. clarified that ckpwrdg_pd# is low for power down current. 4. "output duty cycle, jitter, skew and pll characterisitics" table modifed as follows: a. bypass mode input-to-output skew changed from 3000 to 4500ps to 2550 to 4200ps. typical value reduced from 3500ps to 3370ps. b. separate output-to-output skew spec added for industrial temp. c. additive cycle-to-cycle jitter spec reduced to 1ps max. 5. "phase jitter parameters" modifed as follows: a. corrected typo in pll mode conditions for tjphsgmii. frequency integration range is 1.5mhz to 10mhz. bypass mode conditions were correct. 5-8 c rdw 11/26/2014 1. updated front page text for consistency and updated block diagram resistor colors to highlight internal resistors. 2. updated max frequency of 100mhz pll mode from 110mhz to 140mhz 3. updated max frequency of 125mhz pll mode from 137.5mhz to 175mhz 4. updated max frequency of 50mhz pll mode from 55mhz to 65mhz 5. updated key specifications with addtive phase jitter. 6. added additive phase jitter plot to specifications. various
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